The present invention generally relates to a semiconductor integrated circuit having an emitter follower circuit. The present invention may be suitably used as an output circuit of an emitter coupled logic circuit capable of driving a load having a large capacity.
It is well known that an emitter follower circuit is used as an output circuit of an emitter coupled logic (hereafter simply referred to as ECL). The emitter follower circuit is a low impedance circuit. Therefore as long as a signal is applied to a base terminal of a transistor which constitutes the emitter follower circuit, a current supply is available to an output line with which a load capacitor is coupled. When a potential level at the base terminal of the emitter follower transistor is switched from a low level (hereafter simply referred to as "L") to a high level (hereafter simply referred to "H"), the emitter follower transistor can charge the load capacity at a high speed. On the other hand, when the level of the base terminal of the emitter follower transistor is switched from "H" to "L", a capacity stored in the load capacitor is allowed to be discharged through a resistor connected to an emitter terminal thereof. In this operation, a discharging time necessary for completely discharging the capacity stored in the load capacitor depends on a time constant which is a product of the resistance of the resistor and the capacitance of the load capacitor. For this reason, as the time constant becomes large, the discharging time is increased.
In order to reduce the above problem, an improved ECL circuit has been proposed in the U.S. Pat. No. 4,539,493. The proposed ECL circuit having an emitter follower circuit positively utilizes a fact that when the output of the ECL circuit is switched from "H" to "L", a reverse logic output is switched from "L" to "H", as will be described in detail later. The level change of the reverse logic output is supplied to the base terminal of the emitter follower transistor through a capacitive coupling. Thereby, the base level of the emitter follower transistor is increased, so that the change from "H" to "L" can be facilitated.
However, as will be also described later, the proposed ECL circuit has the following disadvantages. First, although the switching speed of the emitter follower circuit has been increased, it still considerably depends on the load capacitance. It is to be noted that the load capacitance is varied depending on a circuit design and a circuit scale. Therefore, it is very difficult to obtain desired characteristics of the ECL circuit. Secondly, the proposed ECL circuit is apt to be affected by a parastic capacitance coupled with the circuit. Thirdly, it is very difficult to adjust the circuit to obtain desired characteristics.
Yet another ECL circuit has been proposed in the U.S. Pat. No. 4,276,485 in which the reverse output is supplied to the base terminal of the emitter follower transistor through a resistor. The ECL circuit described in the latter publication has also disadvantages similar to those for the former publication.